Increasing demand for high-power semiconductor dies (or “chips”) with larger current carrying capacity has propelled the development of more efficient interconnect designs. Such efficient designs are particularly needed to meet the requirements of dense input/output (“I/O”) and low on-state resistance (“RDSON”) in high-power semiconductor devices. Recent dramatic advances in chip-within-chip integration have been main drivers behind these developments.
The introduction of low-k dielectric materials, ultra-thin wafer metallization, and non-passivated die tops are some of the recent advances that have substantially improved the performance of solid state power devices. Lower loss dielectrics and faster current transmission rates are additional substantial improvements that have been accomplished. Of course, cost continues to be a paramount factor in decisions regarding technology trade-offs, along with technological and performance factors.
Other factors, in addition to cost, are becoming increasingly important. Greater consideration must now also be given to the ever increasing complexity of package interconnect designs. Similarly, increasing market competition is advancing and intensifying the need for high design confidence along with shorter design cycle times.
One key design consideration is simplification of bonding diagrams and bonding processes for die interconnection. For example, conventional device layout for a power metal oxide semiconductor field effect transistor (“power MOSFET”) is limited and is technologically difficult due to the use of conventional contact point arrangements of lead wires connected to the source contact of the power MOSFET. This undesirably causes the RDSON to be increased significantly. In one conventional device layout configuration, for example, a MOSFET connection layout using either gold (“Au”) or aluminum (“Al”) wires for lead-wire connections results in higher spreading resistance, which in turn leads to higher RDSON.
There are several ways to reduce the interconnect resistance and thereby reduce the RDSON. One is by using wire that has a larger diameter, which then mainly reduces the loop resistance contribution. Another is to add or utilize additional wires, which reduces the contribution of the loop resistance and reduces the spreading resistance. That is, the additional wires provide additional bond stitches. The additional bond stitches reduce the average distance between any location on the die top metallization and the nearest bond stitch, thus reducing the spreading resistance.
Unfortunately, such solutions have limits and trade-offs. For example, using larger diameter wire typically creates higher loops, thus increasing costs by requiring more wire material, as well as potentially increasing the overall size of the final package. In addition, in a multiple-wire configuration, the use of a larger wire diameter may require reducing the total number of wires, thus offsetting the gain in cross-section to a significant extent. Further, the addition of more wires reduces the wire bonding throughput of the production line due to the additional assembly operations that are necessitated, or, in the alternative, it requires additional wire bonding equipment that leads to higher device manufacturing costs. These solutions thus run against the competitive market trends of smaller die sizes, higher device current capability, and lower device costs.
As a result, there continues to be a need for improved interconnect designs for achieving lower RDSON, particularly for power MOSFETs which require high gate pulse current during the operation period. A need also remains, particularly in power electronics applications, for improved techniques for addressing both present and future interconnect requirements. Such techniques need to offer the same advantages as bonding using large Al wires, while alleviating or eliminating wire bonding limitations, such as the need to bond a significant number of parallel wires per device in order to fulfill the resistance and current requirements.
Thus, a need still remains for improved interconnect designs and configurations for dies in semiconductor devices. In view of the continuing miniaturization of such devices, and the increasing performance expectations thereof, it is ever more critical that answers be found to these problems.
Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.